This invention relates to semiconductor memory devices and more particularly to an improved input buffer circuit for an MOS random access read/write memory.
Semiconductor memory devices of the type made by the N-channel silicon-gate MOS process and employing one transistor dynamic cells are now the most widely used in computers and digital equipment. A continuing problem in these devices is the input buffer circuits which must detect TTL level address signals, data signals, or controls, and latch these signals so the inputs can change. As the operating speed or access time of memory devices increases, the constraints upon the design of input buffers increases because the rate of switching of the multiplexed addresses is faster so less time is allowed for latching, and noise on the address lines is at a higher level. Use of 5 V rather than 12 V power supplies lowers MOS threshold voltages and causes more difficulty in matching TTL logic levels. Examples of prior input buffers are disclosed in U.S. Pat. No. 4,031,415 issued to Redwine and Kitagawa, and U.S. Pat. No. 4,110,639 issued to Redwine, both assigned to Texas Instruments.
It is the principal object of this invention to provide improved address or data input buffers for a high speed MOS RAM, particularly for a multiplexed-address read/write memory which has TTL compatable inputs. Another object is to provide address buffers which latch rapidly without boosting the inputs and which are noise immune.